1. Field of the Invention
The present invention generally relates to a semiconductor memory device having a plurality of cell array blocks.
2. Description of the Related Art
In a semiconductor memory device such as a masked ROM (read-only memory) having a plurality of cell array blocks, there have been proposed several circuit configurations which reduce the capacitance of conductive lines to achieve high-speed data reading.
For example, in Japanese Patent Unexamined Publication No. 5-167042, the ROM is provided with an ON/OFF switching transistor between a virtual ground line and a bit line or between a bit line and a main bit line so as to select a desired series of memory cells. This can provide linearly arranged main bit lines and virtual ground lines, resulting in reduced capacitance thereof.
Another conventional memory device is disclosed in Japanese Patent Unexamined Publication No. 6-44778. In this device, a memory cell array is divided into a plurality of banks which can be selectively precharged. Since only a selected bank is precharged, the capacitance of a part to be precharged is reduced, resulting in the reduced time required for precharging.